1. Field of the Invention
This invention relates to microprogrammable microprocessors, and more particularly to ROM based microprogrammable microprocessors, and a Universal Serial Bus ("USB") microcontroller development system configured to aid in the design, debug, and testing of USB compliant devices and firmware using a ROM based microprogrammable microprocessor.
2. Discussion of Background
Microprocessor instruction sets are well known in the art. The instruction set of a microprocessor consists of a set of instructions recognized by the microprocessor. Each instruction recognized by the microprocessor is defined in an instruction architectural specification which defines the useful function performed by each instruction and a sequence of actions required to be performed by the microprocessor in order to carry out the instruction. Each instruction in the instruction set is encoded to identify the specific sequence of actions defined by the instruction architectural specification for that instruction.
With the definition of an instruction architectural specification and the encoding of each instruction thereby defined, the microprocessor then has the task of identifying and performing the sequence of actions required to carry out each instruction, thereby implementing the instruction set.
Typically, instruction sets are implemented in either ROM or a set of logic gates. The tradeoff between ROM based instruction sets and gate implementations is the speed at which instructions are retrieved versus the flexibility of implementing new or modified instruction sets. Gate based instruction sets are faster than ROM implementations, but ROM based sets are microprogrammable which makes updating an instruction set as simple as changing the values stored in the ROM.
In many implementations of microprocessors, the interpretation of an instruction byte is performed by combinatorial logic to generate several output terms, each of which gate logic/hardware resources such as Arithmetic Logic Units ("ALUs") and register files. The disadvantage to this approach is that any change in hardware resources or instruction encoding will require redesign and relayout of the combinatorial logic.
FIG. 4 shows a conventional approach to this problem which is to use a read only memory ROM 21 to store the mapping from instruction to decode outputs. For 8 bits of instruction and 15 steps per instruction, mapping requires 2.sup.8 plus 2.sup.4 bits of addressing or 4K words, each of which words needs to be as wide as needed to control all the resources. For the microprocessor described herein, this width is 16 bits.
A 4K.times.16 bit memory can occupy a significant area, and in most technologies this size is larger than the hardware resources it is controlling. This same mapping if synthesized to random gates would be more area efficient, but would suffer from the previously mentioned problem. A method is needed to provide adequate storage for ROM based instructions, but reduce the bit storage requirement for those instructions, thereby making ROM based instruction decoding more size and cost efficient.
Any electronic device utilizing ROM based instruction sets needs to have adequate ROM storage for those instructions. ROM based instruction sets are more size and cost efficient if the amount of ROM storage needed to implement the instruction set can be reduced.
USB is a peripheral bus standard that allows computer peripherals to be attached to a personal computer without the need for specialized cards or other vendor specific hardware attachments. The USB standard specifies a common configuration for the connection of well known peripherals such as CD-ROM, tape and floppy disk drives, scanners, printers, keyboards, joysticks, mice, telephones, modems, etc. In addition to well known peripheral devices, the USB standard has flexibility to accommodate less known and newly developed technologies. Information about the USB standard, including the specification for building USB compliant devices, is currently available free of charge over the Internet.
Developers wishing to implement USB devices must build that device to the USB standard. Prior to fabricating IC's for USB standard devices, a developer will spend a significant amount of resources in testing and refinement of prototypes. An efficient method for testing USB compliant devices is needed to reduce the costs associated with prototype development and testing of those devices.
The design and manufacture of electronic devices such as counters, state machines, specialized registers, and microprocessors is currently aided by technologies that allow engineers to specify design characteristics of a circuit, such as storage device size, register types, connections and associated logic, in a Hardware Description Language ("HDL"). This source code or HDL is then compiled, allowing the electronic device to be simulated and debugged while implementing the specified circuit characteristics. Once the operation of a device is verified, the compiled source code can be mapped to a specific architecture such as Application Specific Integrated Circuits ("ASICs") or Field Programmable Gate Arrays ("FPGAs"). This allows the system designer to produce a device with design flexibility and portability into various architecture families.
As an example, a 3-bit shift register can be implemented in a HDL such as Register Transfer Language ("RTL") with the following RTL statements:
______________________________________ ENTITY shifter3 IS port ( clk : IN BIT; x : IN BIT; q0 : OUT BIT; q1 : OUT BIT; q2 : OUT BIT; END shifter3; ARCHITECTURE struct OF shifter3 IS SIGNAL q0.sub.-- temp, q1.sub.-- temp, q2.sub.-- temp : BIT; BEGIN d1 : DFF PORT MAP (x,clk,q0.sub.-- temp); d2 : DFF PORT MAP (q0.sub.-- temp,clk,q1.sub.-- temp); d3 : DFF PORT MAP (q1.sub.-- temp,clk,q2.sub.-- temp); q0 &lt;= q0.sub.-- temp; q1 &lt;= q1.sub.-- temp; q2 &lt;= q2.sub.-- temp; END struct; ______________________________________
which defines the inputs and outputs of the shifter and then maps those bits to a series of D Flip-Flops. After compiling the source code and debugging the circuit, a netlist can be generated for a specific family of FPGA or ASIC devices to produce the circuit with the desired functionality.